Evaluation of Important Reliability Parameters using VHDL-RTL modelling and Information Flow Approach

Fault tolerance is an essential requirement for critical programming systems, due to potential catastrophic consequences of faults. Several approaches to evaluate system reliability parameters exist today; however, their work is based on the assumptions that hardware and software failures happen independently. The challenge in this field is to take into account the hardware-software interactions in the evaluation of the model. In the continuity of the CETIM project [1] whose principal objective is to define an integrated design of dependable mechatronic systems, this work evaluates important reliability parameters of an embedded application in a stack processor architecture using two dynamic models. The first one (stack processor emulator [2]) allows the study of dynamic performance and the evaluation of a fault-tolerant technique. The second one (information flow approach [3]) evaluates the failure probability for each assembler instruction and for some program loops. The main objective is to estimate the failure probability of the whole application. The hierarchically modelling with the information flow approach makes it possible to evaluate the efficiency of protection program loops. These loops ensure the fault tolerance policy by recovering imminent failures and allow the application to run successfully thanks to a permanent software recover mechanism: in case of a detected and not corrected error, the system returns to the last faultless state. This work is useful because it allows adjusting the architecture and shows the advantages of the hardwaresoftware interactions during the co-design phase before the hardware implementation. It puts the hand on the critical points in term of reliability thanks to the scenarios of critical failure paths in the processor architecture.